PT-2026-65093 · Zephyrproject · Zephyr
CVE-2026-10683
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Publicado
2026-07-27
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Atualizado
2026-07-27
CVSS v3.1
2.4
Baixa
| Vetor | AV:P/AC:L/PR:N/UI:N/S:U/C:N/I:N/A:L |
In the Synopsys DesignWare I2C driver (drivers/i2c/i2c dw.c) operating in target/slave mode, the rx full interrupt handler gates the write requested() callback on dw->state != CMD SEND, and dw->state is only reset to READY on a STOP interrupt. The START DET interrupt, whose handler in i2c dw slave read clear intr bits() would reset the state on every (re)START, was never added to the enabled interrupt mask in i2c dw slave register(), so that recovery path was dead code.
As a result, if the STOP interrupt is lost (bus glitch/reset, or a concurrent master driving STOP) or the bus master issues a legal WRITE-repeated-START-WRITE sequence with the same direction, the driver remains in CMD SEND permanently and never invokes write requested() again for the life of the target.
An I2C master on the same physical bus can deliberately trigger this, causing the I2C target function to malfunction for all subsequent write transactions and desynchronizing consumer framing state (e.g. MCTP-over-I2C), a recoverable-by-reset denial of service of the target peripheral.
The fix unmasks START DET so the state is reset at every bus (re)START. Impact is availability-only over a local board-level bus; no memory corruption results in the in-tree consumer, whose per-byte buffer write is independently bounds-checked.
Correção
Infinite Loop
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