PT-2020-16119 · Xen+3 · Xen+3
Andrew Cooper
·
Published
2020-09-23
·
Updated
2024-06-15
·
CVE-2020-25602
CVSS v3.1
6.0
Medium
| Vector | AV:L/AC:L/PR:H/UI:N/S:C/C:N/I:N/A:H |
Name of the Vulnerable Software and Affected Versions
Xen versions 4.11 through 4.14.x
Description
An issue in Xen allows an x86 PV guest to trigger a host OS crash when handling guest access to the
MSR MISC ENABLE Model Specific Register. This occurs because Xen reads the value from hardware without error handling for a #GP fault, which happens when trying to read this MSR on non-Intel hardware. A malicious PV guest administrator can exploit this to crash Xen, resulting in a host Denial of Service. The vulnerability is specific to x86 systems that do not implement the MISC ENABLE MSR, such as AMD and Hygon systems, while Intel systems are not vulnerable due to their implementation of this MSR.Recommendations
For Xen versions 4.11 through 4.14.x, consider disabling access to the
MSR MISC ENABLE register for x86 PV guests as a temporary workaround to prevent the host OS crash. Ensure that only trusted x86 PV guests are run on the system to minimize the risk of exploitation. At the moment, there is no information about a newer version that contains a fix for this vulnerability.DoS
Improper Handling of Exceptional Conditions
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Weakness Enumeration
Related Identifiers
Affected Products
Linuxmint
Suse
Ubuntu
Xen