PT-2025-46191 · Unknown · Risc-V Rocket-Chip

Published 2025-11-10 · Updated 2025-11-10 · CVE-2025-63384

Positive Technologies (AI Summary)

CVSS v3.1

6.5

Medium

Base vector

AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N

Name of the Vulnerable Software and Affected Versions RISC-V Rocket-Chip versions 1.6 and earlier

Description A flaw exists in the handling of the SRET (Supervisor-mode Exception Return) instruction within the processor. Instead of correctly transitioning from Machine-mode (M-mode) to Supervisor-mode (S-mode) as intended by the sstatus.SPP bit, the processor remains in M-mode. This results in a privilege retention issue.

Recommendations Update to a version of RISC-V Rocket-Chip newer than 1.6.

Exploit

Fix

LPE

Incorrect Privilege Assignment

Weakness Enumeration

CWE-266

Related Identifiers

CVE-2025-63384

Affected Products

Risc-V Rocket-Chip

References · 7

• 🔥 https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET · Exploit
• https://nvd.nist.gov/vuln/detail/CVE-2025-63384 · Security Note
• https://osv.dev/vulnerability/CVE-2025-63384 · Vendor Advisory
• https://t.me/CVEtracker/36954 · Telegram Post
• ❌ https://github.com/chipsalliance/rocket-chip.git · Note, Deleted
• https://twitter.com/VulmonFeeds/status/1987994045235277940 · Twitter Post
• https://twitter.com/CVEnew/status/1987984640364212615 · Twitter Post